The present disclosure relates to semiconductor memory devices and, more particularly, to a block status storage unit of a flash memory device.
Flash memory devices are kinds of nonvolatile memories that are electrically programmable and that are erasable. Flash memory devices provide great interest to many users in applications for large-capacity or coded memories of mobile apparatuses with requirements for higher storage capacity and faster speed of operation. Flash memory devices may be classified into NAND and NOR types. A cell array of the NOR flash memory device is configured such that pluralities of memory cells are connected in parallel to one bit line. On the other hand, in a cell array of the NAND flash memory device, pluralities of memory cells are connected in series to one bit line. Comparing the two types with each other, the NOR flash memory devices are advantageously used in high frequency applications, because they are operable with a fast speed during programming and reading of data relative to the NAND types. A cell array of the NOR flash memory device includes a plurality of blocks forming erasing units. The plurality of blocks constitute a memory bank. A NOR flash memory device with a plurality of memory banks is able to carry out an erasing or a programming operation for one block while conducting a read operation for another block, both at the same time. Generally, the blocks are included in different respective memory banks. Further, a multi-block erasing mode is provided to erase pluralities of blocks, which are each selected by banks, all at a time. Additionally, in the NOR flash memory device, a suspended read mode is provided to carry out a read operation while suspending a writing operation during a period of writing. For these modes, storing and detecting status information to each block is required. Especially, in a flash memory device associated with the multi-block erasing mode or a read-while-write (RWW) mode, there is a need of simultaneously conducting operations for detecting block status information by write and read addresses. FIG. 1A shows a cell structure of a general purpose block status latch for storing and outputting block status information each in response to write and read addresses.
Referring to FIG. 1A, the general purpose block status latch includes a latch loop formed of inverters INV1 and INV2 coupled in opposite directions to each other between first and second nodes N1 and N2. The block status latch further includes set and reset transistors connected to SET and RESET inputs, for storing block status information in the latch loop. A NAND gate G1 outputs status information of the second node N2 in response to a read address RD_ADD, and a NAND gate G2 provides status information to another output terminal in response to a write address WD_ADD. Inverters INV3 and INV4 are respectively connected to outputs of the NAND gates G1 and G2. FIG. 1B shows output circuits summing a plurality of block status information provided from the block status latches shown in FIG. 1A.
Such a structure of a block status latch, which provides block status information independently of the read and write addresses, is disadvantageous to integration density, because the capacity of the flash memory device must be made larger. As the capacity of the flash memory device becomes larger, the number of blocks in a memory cell array also increases. With the increase of the number of blocks, the number of block status latches must also be increased. This means the area occupied by the block status latches in a peripheral circuit of a memory core is also increased. Furthermore, the area of the circuits, such as Summator1, Summator2 in FIG. 1B, summing a plurality of block status information enlarges the whole area of the peripheral circuit.